This invention relates to digital memory systems; and more particularly to, those memory systems which are bit addressable and have variable length data fields stored therein. In bit addressable memories, any single bit may be read from and/or written into the memory. Further, in bit addressable variable length memory systems, any number of contiguous bits starting with the singly addressed bit may be read from and/or written into the memory system.
An exemplary prior art bit addressable variable length memory system is described in U.S. Pat. No. 3,680,058 issued July 25, 1972. A block diagram of that memory system is shown in the patent at FIG. 7. That figure is described in the Detailed Description at column 6 and 7.
One unattractive aspect of the memory there disclosed however, is that it requires too much hardware for its implementation. In particular, that memory requires a register 60 and a shifter 61 which are twice as long as the maximum length field which can be read from the memory.
Thus for example, if the maximum length field that can be read is 64 bits long, then register 60 must be able to hold 128 bits and shifter 61 must be able to shift 128 bits. Clearly, a memory architecture which requires a shorter length for register 60 and shifter 61 would be a much more attractive design.
Another undesirable feature of U.S. Pat. No. 3,680,058 memory is that all writes thereto must be preceeded by a read. Clearly, this requirement substantially slows down the memory's operation. However, the reads are required by the design in order that the bits which are adjacent to those to be written can remain unchanged.
Therefore, a primary object of the invention is to provide an improved bit addressable variable length memory system.
Another object of the invention is to provide a bit addressable variable length memory system that uses substantially less hardware for its implementation than prior art designs used.
Still another object of the invention is to provide a bit addressable variable length memory system wherein writes to the memory are performed without any read therefrom.